The present invention relates to a semiconductor memory device such as a DRAM (Dynamic Random Access Memory), an SRAM (Static Random Access Memory) or the like, and a repair search method and a self-repair method in the semiconductor memory device, and particularly to a semiconductor memory device including a redundancy search circuit for replacing faulty (defective) memory cells with redundant memory cells included in advance, and a repair search method and a self-repair method in the semiconductor memory device.
With a recent great increase in a degree of integration of semiconductor memory devices such as DRAMs and the like, yield has become a challenge in manufacturing. It is nearly impossible in practice to raise yields to 100%; it is assumed in a present situation that faulty memory cells (hereinafter referred to occasionally as abnormal bits) exist.
When there are faulty memory cells, however, the semiconductor memory device cannot be shipped as a product, of course.
Accordingly, in practice, a number of spare memory cells are provided. When a faulty memory cell is found, the faulty memory cell is replaced with a spare memory cell to repair the faulty chip.
Specifically, the repair is realized by providing spare memory cells as redundant cells and if there is a faulty memory cell, replacing the faulty memory cell with a spare memory cell in a unit of a bit line or an address line. Whether memory cells are good or faulty is conventionally determined by using an external memory tester in a stage of shipment from a factory.
On the other hand, with recent dramatic improvement in LSI technology, there have been increasing cases where a plurality of memories and logic units are simultaneously mounted on an LSI chip in a mixed manner. It has therefore become actually difficult to test individual memories independently. In addition, with faster performance speed of LSI, it is difficult to test and evaluate the individual memories using an external memory tester. Therefore, a memory test method incorporated in an LSI has become essential. Even if the individual memories can be tested and evaluated using an external memory tester, such a memory tester is very expensive. Hence, as cost of testing in LSI manufacturing has recently been increasing very much, a method that enables high-speed testing at performance speed of LSI and can be realized inexpensively is desired in a current situation.
As described above, in testing and evaluation of a semiconductor memory device, whether memory cells are good or faulty is evaluated bit by bit (memory cell by memory cell). A part included in an LSI to perform the evaluation is generally referred to as a BIST (built-in self-test) circuit. Commercially available test circuits are mainly for SRAMs in a current situation. While there are some test circuits commercially available for DRAMs, each manufacturer develops test circuits for their own DRAM architecture.
A BIST circuit determines whether the memory has an abnormal (defective or faulty) bit, and when there is an abnormal bit, the BIST circuit determines an address of the bit (memory cell). The semiconductor memory device is provided with dummy bit lines and word lines for repairing abnormal bits found by the BIST circuit.
The dummy bit lines and word lines are referred to as redundant lines. The BIST circuit performs processing only for finding abnormal bits. Hence, subsequent processing determines actually how to use the redundant lines.
A plurality of redundant lines are provided in a column direction and a row direction. It is therefore necessary to determine which abnormal bit is to be replaced by which redundant line. This replacement of an abnormal bit with one of the redundant lines is referred to as repair. A process of determining which redundant line is to be used to replace the abnormal bit is referred to as repair search. Completing the repair on the chip on the basis of a result of the search is referred to as self-repair.
In the case of using an external memory tester, an external memory tester computer is used to perform calculation for repair search (see Patent Document 1, for example). Alternatively, a built-in BIST circuit is provided with not only an evaluation function for determining whether there is an abnormal bit but also a repair search (redundancy analysis) function for determining which redundant line is to be used to replace the abnormal bit (see Patent Document 2, for example).
[Patent Document 1]
Japanese Patent Laid-Open No. Hei 7-146340
[Patent Document 2]
Japanese Patent Laid-Open No. 2002-117697
However, even in the case of an LSI including a BIST circuit, when information of each abnormal bit is taken out to the outside and calculation is performed by an external computer as in a conventional technique described in Patent Document 1, a memory of the external computer has information on normality/abnormality of bits at all addresses. Thus a capacity of the memory is significantly consumed, and also calculation takes much time.
In the case where a built-in BIST circuit is provided with a repair search function as in a conventional technique described in Patent Document 2, a plurality of combinations (six combinations in this example) are considered as combinations enabling repair. Since a method is employed in which locations for storing addresses for all the combinations are provided and repairability is determined simultaneously for all the six combinations, it is considered that a circuit scale accordingly becomes large.